1. Field of the Invention
The present invention relates to a semiconductor device including wiring and a manufacturing method thereof.
2. Description of the Related Art
To increase packaging density of a semiconductor device, a method is used in which a semiconductor construct, referred to as a chip size package (CSP), is provided on a base plate having a planar size that is greater than that of the semiconductor construct. Japanese Patent Application Laid-Open (Kokai) Publication No. 2004-71998 discloses the configuration of a semiconductor device such as this and a manufacturing method thereof. In the semiconductor device disclosed in this patent publication, an insulating layer is provided on a base plate around a periphery of a semiconductor construct, and an upper-layer insulating film is provided on the semiconductor construct and the insulating layer. An upper-layer wiring connected to the external connection electrode (columnar electrode) of the semiconductor construct is provided on the upper-layer insulating film.
In the manufacturing method of the above-described conventional semiconductor device, a plurality of semiconductor constructs are disposed on the base plate of which the size allows a plurality of completed semiconductor devices to be formed thereon, and the insulating layer and the upper-layer insulating film are formed. Then, the upper-layer wiring is formed on the upper-layer insulating film. Therefore, when the upper-layer wiring is formed on the upper-layer insulating film, the semiconductor constructs are already embedded under the upper-layer insulating film.
Therefore, after the formation of the upper-layer wiring, when the upper-layer wiring is inspected and judged to be defective, non-defective semiconductor constructs that are relatively expensive which are embedded under the upper-layer insulating film under the upper-layer wiring judged to be defective must be discarded. As a result, in view of the yield rate of the semiconductor device configured as described above, yield requirements of upper-layer wiring formation becomes more difficult to achieve.
For example, the yield rate of wiring formation with a 50 μm to 70 μm rule is currently 80% to 85%. The yield rate in terms of the cost aspect of the semiconductor device configured as described above is said to be 99.5% or more, and cannot be satisfied. With the miniaturization of wiring, a method that can be applied to a 30 μm to 50 μm rule and a 15 μm to 25 μm rule is especially required.